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.arm	__HEADENTRY(stext) ARM_BE8(setend	be )			@ ensure we are in BE8 mode THUMB(	adr	r9, BSYM(1f)	)	@ Kernel is always entered in ARM. THUMB(	bx	r9		)	@ If this is a Thumb-2 kernel, THUMB(	.thumb			)	@ switch to Thumb now. THUMB(1:			)#ifdef CONFIG_ARM_VIRT_EXT	bl	__hyp_stub_install#endif	@ ensure svc mode and all interrupts masked	safe_svcmode_maskall r9	mrc	p15, 0, r9, c0, c0		@ get processor id	bl	__lookup_processor_type		@ r5=procinfo r9=cpuid	movs	r10, r5				@ invalid processor (r5=0)?，r10记录了proc_info_list结构地址 THUMB( it	eq )		@ force fixup-able long branch encoding	beq	__error_p			@ yes, error 'p'#ifdef CONFIG_ARM_LPAE	mrc	p15, 0, r3, c0, c1, 4		@ read ID_MMFR0	and	r3, r3, #0xf			@ extract VMSA support	cmp	r3, #5				@ long-descriptor translation table format? THUMB( it	lo )				@ force fixup-able long branch encoding	blo	__error_lpae			@ only classic page table format#endif#ifndef CONFIG_XIP_KERNEL	adr	r3, 2f	ldmia	r3, {r4, r8}	sub	r4, r3, r4			@ (PHYS_OFFSET - PAGE_OFFSET)	add	r8, r8, r4			@ PHYS_OFFSET#else	ldr	r8, =PLAT_PHYS_OFFSET		@ always constant in this case#endif	/*	 * r1 = machine no, r2 = atags or dtb,	 * r8 = phys_offset, r9 = cpuid, r10 = procinfo	 */	bl	__vet_atags#ifdef CONFIG_SMP_ON_UP	bl	__fixup_smp#endif#ifdef CONFIG_ARM_PATCH_PHYS_VIRT	bl	__fixup_pv_table#endif	bl	__create_page_tables	/*	 * The following calls CPU specific code in a position independent	 * manner.  See arch/arm/mm/proc-*.S for details.  r10 = base of	 * xxx_proc_info structure selected by __lookup_processor_type	 * above.  On return, the CPU will be ready for the MMU to be	 * turned on, and r0 will hold the CPU control register value.	 */	ldr	r13, =__mmap_switched		@ address to jump to after						@ mmu has been enabled	adr	lr, BSYM(1f)			@ return (PIC) address	mov	r8, r4				@ set TTBR1 to swapper_pg_dir ARM(	add	pc, r10, #PROCINFO_INITFUNC	) @ __v7_setup THUMB(	add	r12, r10, #PROCINFO_INITFUNC	) THUMB(	mov	pc, r12				)1:	b	__enable_mmuENDPROC(stext)	.ltorg

__v7_setup:	adr	r12, __v7_setup_stack		@ the local stack	stmia	r12, {r0-r5, r7, r9, r11, lr}@ 寄存器入栈__v7_setup_stack是个11个word的局部栈，就在本函数后面定义，stmia表明此处用的是递增栈；	bl      v7_flush_dcache_louis @ 清除数据缓存	ldmia	r12, {r0-r5, r7, r9, r11, lr} @ 寄存器出栈	mrc	p15, 0, r0, c0, c0, 0		@ read main ID register	and	r10, r0, #0xff000000		@ ARM?	teq	r10, #0x41000000	bne	3f	and	r5, r0, #0x00f00000		@ variant	and	r6, r0, #0x0000000f		@ revision	orr	r6, r6, r5, lsr #20-4		@ combine variant and revision	ubfx	r0, r0, #4, #12			@ primary part number@ Cortex-A7 primary part number == 0xc07	/* Cortex-A8 Errata */	ldr	r10, =0x00000c08		@ Cortex-A8 primary part number	teq	r0, r10	bne	2f#if defined(CONFIG_ARM_ERRATA_430973) && !defined(CONFIG_ARCH_MULTIPLATFORM)	teq	r5, #0x00100000			@ only present in r1p*	mrceq	p15, 0, r10, c1, c0, 1		@ read aux control register	orreq	r10, r10, #(1 << 6)		@ set IBE to 1	mcreq	p15, 0, r10, c1, c0, 1		@ write aux control register#endif#ifdef CONFIG_ARM_ERRATA_458693	teq	r6, #0x20			@ only present in r2p0	mrceq	p15, 0, r10, c1, c0, 1		@ read aux control register	orreq	r10, r10, #(1 << 5)		@ set L1NEON to 1	orreq	r10, r10, #(1 << 9)		@ set PLDNOP to 1	mcreq	p15, 0, r10, c1, c0, 1		@ write aux control register#endif#ifdef CONFIG_ARM_ERRATA_460075	teq	r6, #0x20			@ only present in r2p0	mrceq	p15, 1, r10, c9, c0, 2		@ read L2 cache aux ctrl register	tsteq	r10, #1 << 22	orreq	r10, r10, #(1 << 22)		@ set the Write Allocate disable bit	mcreq	p15, 1, r10, c9, c0, 2		@ write the L2 cache aux ctrl register#endif	b	3f	/* Cortex-A9 Errata */2:	ldr	r10, =0x00000c09		@ Cortex-A9 primary part number	teq	r0, r10	bne	3f#ifdef CONFIG_ARM_ERRATA_742230	cmp	r6, #0x22			@ only present up to r2p2	mrcle	p15, 0, r10, c15, c0, 1		@ read diagnostic register	orrle	r10, r10, #1 << 4		@ set bit #4	mcrle	p15, 0, r10, c15, c0, 1		@ write diagnostic register#endif#ifdef CONFIG_ARM_ERRATA_742231	teq	r6, #0x20			@ present in r2p0	teqne	r6, #0x21			@ present in r2p1	teqne	r6, #0x22			@ present in r2p2	mrceq	p15, 0, r10, c15, c0, 1		@ read diagnostic register	orreq	r10, r10, #1 << 12		@ set bit #12	orreq	r10, r10, #1 << 22		@ set bit #22	mcreq	p15, 0, r10, c15, c0, 1		@ write diagnostic register#endif#ifdef CONFIG_ARM_ERRATA_743622	teq	r5, #0x00200000			@ only present in r2p*	mrceq	p15, 0, r10, c15, c0, 1		@ read diagnostic register	orreq	r10, r10, #1 << 6		@ set bit #6	mcreq	p15, 0, r10, c15, c0, 1		@ write diagnostic register#endif#if defined(CONFIG_ARM_ERRATA_751472) && defined(CONFIG_SMP)	ALT_SMP(cmp r6, #0x30)			@ present prior to r3p0	ALT_UP_B(1f)	mrclt	p15, 0, r10, c15, c0, 1		@ read diagnostic register	orrlt	r10, r10, #1 << 11		@ set bit #11	mcrlt	p15, 0, r10, c15, c0, 1		@ write diagnostic register1:#endif	/* Cortex-A15 Errata */3:	ldr	r10, =0x00000c0f		@ Cortex-A15 primary part number	teq	r0, r10	bne	4f#ifdef CONFIG_ARM_ERRATA_773022	cmp	r6, #0x4			@ only present up to r0p4	mrcle	p15, 0, r10, c1, c0, 1		@ read aux control register	orrle	r10, r10, #1 << 1		@ disable loop buffer	mcrle	p15, 0, r10, c1, c0, 1		@ write aux control register#endif4:	mov	r10, #0	mcr	p15, 0, r10, c7, c5, 0		@ I+BTB cache invalidate#ifdef CONFIG_MMU	mcr	p15, 0, r10, c8, c7, 0		@ invalidate I + D TLBs（Translation Lookaside Buffer）	v7_ttb_setup r10, r4, r8, r5		@ TTBCR（Translation Table Base Control Register）, TTBRx setup	ldr	r5, =PRRR			@ PRRR（Primary Region Remap Register）	ldr	r6, =NMRR			@ NMRR（Normal Memory Remap Register,）	mcr	p15, 0, r5, c10, c2, 0		@ write PRRR	mcr	p15, 0, r6, c10, c2, 1		@ write NMRR#endif	dsb					@ Complete invalidations#ifndef CONFIG_ARM_THUMBEE	mrc	p15, 0, r0, c0, c1, 0		@ read ID_PFR0 for ThumbEE	and	r0, r0, #(0xf << 12)		@ ThumbEE enabled field	teq	r0, #(1 << 12)			@ check if ThumbEE is present	bne	1f	mov	r5, #0	mcr	p14, 6, r5, c1, c0, 0		@ Initialize TEEHBR to 0	mrc	p14, 6, r0, c0, c0, 0		@ load TEECR	orr	r0, r0, #1			@ set the 1st bit in order to	mcr	p14, 6, r0, c0, c0, 0		@ stop userspace TEEHBR access1:#endif	adr	r5, v7_crval /* AT  * TFR EV X F I D LR S  * .EEE ..EE PUI. .T.T 4RVI ZWRS BLDP WCAM  * rxxx rrxx xxx0 0101 xxxx xxxx x111 xxxx < forced  * 1 0 110 0011 1100 .111 1101 < we want  */ /* .type v7_crval, #object  v7_crval:  crval clear=0x0120c302, mmuset=0x10c03c7d, ucset=0x00c01c7c */	ldmia	r5, {r5, r6} @ [r5] = clear,[r6] = mmuset ARM_BE8(orr	r6, r6, #1 << 25)		@ big-endian page tables#ifdef CONFIG_SWP_EMULATE	orr     r5, r5, #(1 << 10)              @ set SW bit in "clear"	bic     r6, r6, #(1 << 10)              @ clear it in "mmuset"#endif   	mrc	p15, 0, r0, c1, c0, 0		@ read control register	bic	r0, r0, r5			@ clear bits them	orr	r0, r0, r6			@ set them@ r0已经使能了mmu，但是并没有写入CP15，这个操作由__enable_mmu函数来完成。 THUMB(	orr	r0, r0, #1 << 30	)	@ Thumb exceptions	mov	pc, lr				@ return to head.S:__retENDPROC(__v7_setup)

clear和set c1, System Control Register (SCTLR)，包括Exception Endianness bit、Interrupt Vectors Enable bit、Vectors bit.、I-cache D-cache enable、MMU enable bit等。Vectors bit决定了异常向量的入口是0x0，还是0xffff0000。

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